`include "chunjun_define.sv" 
`include "chunjun_lib_define.sv" 

//================================================================================================
// File Name   : vtcu_bank_router_gather.sv
// Create Time : Mon Jan  6 11:06:17 2025
// Description : Gather out the final rdata from the BANK_N output. Need to use the destination-onehot-array generated from sactter.
// 
//================================================================================================

module vtcu_bank_router_gather  #(parameter BANK_N      = `CHUNJUN_VTCM_BANK_N      ,
                                            BANK_DATA_W = 32                        , // do not modify this param at this version
                                            DATA_W      = 64                        ,
                                            MODE        = 2'b00                     , // do not modify this param at this version
                                            N           = DATA_W/BANK_DATA_W
) (
input   logic [BANK_N-1:0]                      rsp_vld,
input   logic [BANK_N-1:0][BANK_DATA_W-1:0]     rsp_rdata,
input   logic [BANK_N-1:0][N-1:0]               rsp_rdata_dest_oh,

output  logic [DATA_W-1:0]                      origin_rdata              
);

genvar i;
integer x;
 
generate
if(MODE==2'b00) begin : GEN_GATHER_MODE0
    for(i=0;i<N;i=i+1)begin: GEN_RDATA_LOOP0
        always @(*) begin
            origin_rdata[BANK_DATA_W*i +: BANK_DATA_W] = 'h0;
            for(x=0;x<BANK_N;x=x+1)begin: GEN_RDATA_LOOP1
                origin_rdata[BANK_DATA_W*i +: BANK_DATA_W]    = origin_rdata[BANK_DATA_W*i +: BANK_DATA_W] | ({BANK_DATA_W{rsp_rdata_dest_oh[x][i] && rsp_vld[x]}} & rsp_rdata[x]);  
            end
        end
    end
end
else begin : GEN_GATHER_MODEX
    assign origin_rdata = 'h0;
end
endgenerate
 
endmodule

`include "chunjun_undefine.sv" 
